The semiconductor industry has progressed into smaller technology node processes in pursuit of higher device density, higher performance, and lower costs. One process for improved device performance includes creating an epitaxy region for the source/drain for enhanced transistor device performance. The epitaxy region provides a strained region that enhances carrier mobility.
Typically isolation regions such as shallow trench isolation (STI) features are used to separate adjacent n-type and p-type transistors. However, the STI feature may cause the epitaxially grown material to form a facet at or near the STI edge (or sidewall). These unwanted facets can impact subsequent processing including, for example, the formation of a contact. For example, silicide, which is typical of contact formation, may be improperly formed on the epitaxy region. Such problems may lead to device performance issues including increases in leakage currents.
Therefore, what is needed is a device and method providing for reduced and/or eliminated facet-formation.